1. Field
The embodiment relates to a clock selection circuit and a synthesizer.
2. Description of the Related Art
The recent improvement in the performance and the packing densities in the integrated electronic circuits requires each chip to exhibit higher performance. Even the synthesizers which supply to various circuits clock signals being necessary for operation of the circuits and having frequencies necessary for the operation are required to concurrently satisfy a number of requirements such as bandwidth broadening, narrowing of frequency gaps, improvement of noise characteristics, and the like.
In a synthesizer which has been proposed in the above circumstances, a plurality of clock signals are prepared in a circuit, and one of the clock signals having a desired frequency and desired noise characteristics is selected and outputted. (See Japanese Unexamined Patent Publication No. 2001-339301).
FIG. 13 is a block diagram illustrating a conventional synthesizer. As illustrated in FIG. 13, the synthesizer 100 comprises a phase comparator 101, an LPF (low-pass filter) 102, a voltage-controlled-oscillator (VCO) group 103, a frequency divider 104, and a clock selection circuit 105. Hereinafter, the voltage controlled oscillator is referred to as the VCO, and the voltage-controlled-oscillator group is referred to as the VCO group.
A reference clock signal REF outputted from, for example, a quartz oscillator and a frequency-divided clock signal outputted from the frequency divider 104 are inputted into the phase comparator 101. The phase comparator 101 detects a phase difference between the reference clock signal REF and a frequency-divided clock signal, and outputs a phase-difference signal. Only a low-frequency component of the phase-difference signal passes through the LPF 102, so that the LPF 102 outputs to the VCO group 103 a voltage corresponding to the phase difference between the reference clock signal REF and the frequency-divided clock signal.
The VCO group 103 contains a plurality of VCOs (VCO1 to VCO15). Generally, the number of the VCOs is designed to have 2^N−1, and 15 in this example. The clock selection circuit 105 selects one of the VCOs in the VCO group 103 so that the selected VCO outputs a clock signal CLK having a frequency corresponding to the voltage outputted from the LPF 102. The clock signal CLK is supplied to the frequency divider 104 and the outside of the synthesizer 100. The frequency divider 104 divides the frequency of the clock signal CLK. The frequency-division ratio can be changed in accordance with an external instruction.
The reference clock signal REF and the frequency-divided clock signal CLK are inputted into the clock selection circuit 105. The clock selection circuit 105 selects one of the VCOs in the VCO group 103 so that the frequency-divided clock signal CLK outputted from the frequency divider 104 has the most appropriate frequency. The clock selection circuit 105 selects a VCO which minimizes the frequency difference between the reference clock signal REF and the frequency-divided clock signal, according to the frequency-division ratio of the frequency divider 104.
Next, the sequence of selecting a VCO by the clock selection circuit 105 is explained in detail below. FIG. 14 is a diagram presented for explaining the sequence of selecting a VCO by the clock selection circuit 105. The oblique lines in FIG. 14 indicate the characteristics of the VCO1 to VCO15 in the VCO group 103. The oblique line at the bottom indicates the characteristic of the VCO1, and the oblique line at the top indicates the characteristic of the VCO15. The VCO which is to be selected for the currently set frequency-division ratio is indicated as “Target.” When the VCO indicated as “Target” is selected, the frequency of the frequency-divided clock signal outputted from the frequency divider 104 becomes closest to the frequency of the reference clock signal REF. The clock selection circuit 105 selects one of the VCO1 to VCO15 according to a code. The value of the code is proportional to the number of the selected one of the VCO1 to VCO15.
The clock selection circuit 105 first selects the VCO8 in the center of the array of VCO1 to VCO15 according to the code “8” as indicated by the blank circle in FIG. 14, and it is determined whether the frequency of the clock signal outputted from the target VCO (corresponding to the reference clock signal REF) is higher or lower than the frequency of the clock signal outputted from the selected VCO8 (corresponding to the frequency of the frequency-divided clock signal outputted from the frequency divider 104). Then, the code is changed by ±4 according to the determination result. Thereafter, the selected VCO is changed in a similar manner by repeating the determination whether the frequency of the clock signal outputted from the target VCO is higher or lower than the frequency of the clock signal outputted from the selected VCO, and changing the code by ±2 and then ±1 until the selected VCO reaches the target VCO. That is, a binary search is performed.
In the example of FIG. 14, the frequency of the target clock signal is higher than the frequency of the clock signal outputted from the selected VCO8. Therefore, the clock selection circuit 105 changes the code by +4, so that the VCO12 is selected. At this time, the frequency of the target clock signal is still higher than the frequency of the clock signal outputted from the selected VCO12. Thus, the clock selection circuit 105 changes the code by +2, so that the VCO14 is selected. At this time, the frequency of the target clock signal is lower than the frequency of the clock of the VCO8. Therefore, the clock selection circuit 105 changes the code by −1, so that the VCO13 is selected as the target VCO.
Next, details of the clock selection circuit 105 are explained below. FIG. 15 is a circuit diagram of a conventional clock selection circuit. As illustrated in FIG. 15, the clock selection circuit 105 comprises counters 111 and 112, a difference calculation unit 113, a comparison unit 114, a count-error-margin unit 115, a phase-information addition unit 116, a phase information unit 117, a timer counter 118, a timing TB (table) 119, a phase change unit 120, a reset-signal output unit 121, a clock-selection-signal output unit 122, a shift TB 123, an end-of-selection determination unit 124, and an optimum-clock-information output unit 125. In addition, the frequency divider 104, the VCO group 103, and the reference clock signal REF, which are indicated in FIG. 13, are also indicated in FIG. 15.
The counter 111 counts clock pulses in the frequency-divided clock signal outputted from the frequency divider 104. The counter 112 counts clock pulses in the reference clock signal REF. The difference calculation unit 113 obtains the difference between the count of clock pulses in the frequency-divided clock signal obtained by the counter 111 and the count of clock pulses in the reference clock signal REF obtained by the counter 112.
When the comparison unit 114 receives a comparison-instruction signal from the timer counter 118, the comparison unit 114 compares the count of clock pulses in the frequency-divided clock signal (the frequency of the frequency-divided clock signal) and the count of clock pulses in the reference clock signal REF (the frequency of the reference clock signal REF), and determines whether or not the counts are equal, or which count is greater, on the basis of the difference value outputted from the difference calculation unit 113. When the difference value is within a range indicated by the count-error-margin unit 115, the comparison unit 114 determines that the counts obtained by the counters 111 and 112 are equal. Since the reference clock signal REF and the frequency-divided clock signal are asynchronous, the timings of rising and falling of the reference clock signal REF and the frequency-divided clock signal can drift, so that errors which can occur in the counts should be considered.
When the comparison unit 114 outputs a comparison result, the phase-information addition unit 116 increments by one the phase information held by the phase information unit 117. The phase information indicates a layer in which a comparison of the frequency-divided clock signal and the reference clock signal REF is currently made during the sequence of the binary search, and the number of times the VCO has been changed. The phase information indicates the number “0” when the code is “8,” the phase information indicates the number “1” when the code is changed by “±4,” the phase information indicates the number “2” when the code is changed by “±2,” the phase information indicates the number “3” when the code is changed by “±1.”
When the reset-signal output unit 121 outputs a reset signal, the timer counter 118 counts from zero the clock pulses in the reference clock signal REF. When the count reaches a value indicated by the timing TB 119, the timer counter 118 outputs to the comparison unit 114 a comparison-instruction signal.
The timing TB 119 stores the values of the count corresponding to each phase. For example, the timing TB 119 stores the count value W for the phase “0,” the count value W for the phase “1,” . . . , the count value W for the phase “n” so that the comparison-instruction signal is outputted at regular intervals. The time intervals are determined so that a difference occurs between the counts of clock pulses outputted from VCOs having adjacent frequencies in each interval, i.e., a difference occurs between the counts obtained by the counters 111 and 112 in an interval even when a VCO next to the target VCO is selected (for example, after one or more selections are made at one or more phases).
When the phase information held by the phase information unit 117 is updated, the phase change unit 120 outputs a signal indicating the update to the reset-signal output unit 121, the clock-selection-signal output unit 122, and the end-of-selection determination unit 124. The reset-signal output unit 121 outputs a reset signal to the counters 111 and 112 and the timer counter 118 on receipt of the signal from the phase change unit 120, so that the counts of the counters 111 and 112 and the timer counter 118 are reset to zero. When the clock-selection-signal output unit 122 receives the above signal from the phase change unit 120, the clock-selection-signal output unit 122 refers to the shift TB 123, and acquires the amount of a code to be changed, on the basis of the phase information and the result of the comparison made by the comparison unit 114. The shift TB 123 indicates the amounts of change in the code corresponding to the phase information. For example, the amount of change in the code stored in the shift TB 123 is ±4 when the phase is “1,” ±2 when the phase is “2,” and ±1 when the phase is “3.”
Since the initial value of the phase information is “0,” the clock-selection-signal output unit 122 outputs the value “8” of the code so that the VCO8 in the center of the VCO group 103 is selected. Therefore, when the comparison result is outputted from the comparison unit 114, the phase information becomes “1,” and the clock-selection-signal output unit 122 changes the code by “+4” or “−4” according to the comparison result and the phase information. Thereafter, the code is changed so that the target VCO is finally selected.
In order to determine whether or not the sequence of selecting a VCO is completed, the end-of-selection determination unit 124 determines whether or not the phase information held by the phase information unit 117 is the final value of the phase information plus one. For example, in the case where the number of the VCOs is 15, the sequence of selecting a VCO is completed when the phase information is “3.” Therefore, when the phase information is “4,” the end-of-selection determination unit 124 determines that the sequence of selecting a VCO is completed. When the optimum-clock-information output unit 125 receives the determination by the end-of-selection determination unit 124, the optimum-clock-information output unit 125 externally outputs a signal indicating the completion of the sequence of selecting an optimum VCO, although the output of this information from the clock selection circuit 105 is not shown in FIG. 13.
Next, the operations of the clock selection circuit 105 of FIG. 15 are explained with reference to a flowchart. FIG. 16 is a flowchart indicating the operations of the clock selection circuit of FIG. 15.
In step S111, the timer counter 118 in the clock selection circuit 105 starts counting. When the count reaches the value corresponding to the phase “1” and being stored in the timing TB 119, the timer counter 118 outputs a comparison-instruction signal to the comparison unit 114. In this example, it is assumed that, at this time, the phase information is “0,” and the VCO8 is selected.
When the comparison unit 114 receives the comparison-instruction signal from the timer counter 118, the comparison unit 114 determines whether the frequency of the selected VCO8 (the count of clock pulses outputted from the selected VCO8) is higher or lower than the frequency of the target clock signal (the count of clock pulses in the target clock signal). The phase-information addition unit 116 increments by one the phase information “0” held by the phase information unit 117.
In step S112, when the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S113. When the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S114.
In step S113, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “1,” and the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the code is changed by “+4.”
In step S114, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “1,” and the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the code is changed by “−4.”
In step S115, when the count of the timer counter 118 in the clock selection circuit 105 reaches the value corresponding to the phase “2” and being stored in the timing TB 119, the timer counter 118 outputs a comparison-instruction signal to the comparison unit 114. At this time, the phase of the clock selection circuit 105 is “1.”
When the comparison unit 114 receives the comparison-instruction signal from the timer counter 118, the comparison unit 114 determines whether the frequency of the selected VCO (the count of clock pulses outputted from the selected VCO) is higher or lower than the frequency of the target clock signal (the count of clock pulses in the target clock signal). The phase-information addition unit 116 increments by one the phase information “1” held by the phase information unit 117.
In step S116, when the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S117. When the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S118.
In step S117, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “2,” and the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the code is changed by “+2.”
In step S118, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “2,” and the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the code is changed by “−2.”
In step S119, when the count of the timer counter 118 in the clock selection circuit 105 reaches the value corresponding to the phase “3” and being stored in the timing TB 119, the timer counter 118 outputs a comparison-instruction signal to the comparison unit 114. At this time, the phase of the clock selection circuit 105 is “2.”
When the comparison unit 114 receives the comparison-instruction signal from the timer counter 118, the comparison unit 114 determines whether the frequency of the selected VCO (the count of clock pulses outputted from the selected VCO) is higher or lower than the frequency of the target clock signal (the count of clock pulses in the target clock signal). The phase-information addition unit 116 increments by one the phase information “2” held by the phase information unit 117.
In step S120, when the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S121. When the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the operation of the clock-selection-signal output unit 122 goes to step S122.
In step S121, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “3,” and the comparison unit 114 determines that the frequency of the selected VCO is lower than the frequency of the target VCO, the code is changed by “+1.”
In step S122, the clock-selection-signal output unit 122 acquires from the shift TB 123 the amount of change in the code on the basis of the phase information held in the phase information unit 117 and the result of the comparison made by the comparison unit 114. Since the phase information is “3,” and the comparison unit 114 determines that the frequency of the selected VCO is higher than the frequency of the target VCO, the code is changed by “−1.”
In step S123, when the count of the timer counter 118 in the clock selection circuit 105 reaches the value corresponding to the phase “4” and being stored in the timing TB 119, the timer counter 118 outputs a comparison-instruction signal to the comparison unit 114. At this time, the phase of the clock selection circuit 105 is “3.”
When the comparison unit 114 receives the comparison-instruction signal from the timer counter 118, the comparison unit 114 determines whether the frequency of the selected VCO (the count of clock pulses outputted from the selected VCO) is higher or lower than the frequency of the target clock signal (the count of clock pulses in the target clock signal). The phase-information addition unit 116 increments by one the phase information “3” held by the phase information unit 117.
Since the phase information is “4,”, the end-of-selection determination unit 124 determines that the sequence of selecting a VCO is completed. When the phase information becomes “4,” the phase change unit 120 controls the clock-selection-signal output unit 122 so as not to newly select a VCO.
As explained above, the clock selection circuit 105 can select an optimum VCO.
Next, the characteristics of the VCO group 103 of FIG. 13 are explained. The VCO group 103 uses LC-resonance type VCOs because of their superior noise characteristics. In the VCO group 103, the plurality of VCOs are realized (as a plurality of clock sources) by switching among a plurality of capacitors according to the code. However, since the relationship between the frequency and the capacitance is nonlinear, the gaps between the VCOs are not equal as illustrated in FIG. 14.
FIG. 17 is a diagram presented for explaining the characteristics of the VCO group 103. The oblique lines in FIG. 17 indicate the characteristics of the VCO group 103. As indicated in FIG. 17, the gaps between the clock frequencies decrease with the frequencies. The comparison time, which is a time necessary for comparison of a selected VCO and the target VCO, is determined by the minimum frequency gap. When the minimum frequency gap is indicated as fg_min, the comparison time is indicated as 1/fg_min. Since the determination is required to be made N times until the target VCO is selected from among the 2^N−1 VCOs, the time necessary for the sequence of selecting the VCO is N/fg_min.